diff --git a/src/hotspot/cpu/riscv/c2_CodeStubs_riscv.cpp b/src/hotspot/cpu/riscv/c2_CodeStubs_riscv.cpp
index 7a00f2e7c69..d1c66ce1da7 100644
--- a/src/hotspot/cpu/riscv/c2_CodeStubs_riscv.cpp
+++ b/src/hotspot/cpu/riscv/c2_CodeStubs_riscv.cpp
@@ -60,10 +60,13 @@ int C2EntryBarrierStub::max_size() const {
 
 void C2EntryBarrierStub::emit(C2_MacroAssembler& masm) {
   __ bind(entry());
+  RuntimeAddress target(StubRoutines::method_entry_barrier());
+  __ relocate(target.rspec(), [&] {
+    int32_t offset;
+    __ la_patchable(t0, target, offset);
+    __ jalr(ra, t0, offset);
+  });
 
-  int32_t offset = 0;
-  __ movptr(t0, StubRoutines::method_entry_barrier(), offset);
-  __ jalr(ra, t0, offset);
   __ j(continuation());
 
   // make guard value 4-byte aligned so that it can be accessed by atomic instructions on RISC-V
diff --git a/src/hotspot/cpu/riscv/gc/shared/barrierSetAssembler_riscv.cpp b/src/hotspot/cpu/riscv/gc/shared/barrierSetAssembler_riscv.cpp
index a9ac129efc0..a4440890b09 100644
--- a/src/hotspot/cpu/riscv/gc/shared/barrierSetAssembler_riscv.cpp
+++ b/src/hotspot/cpu/riscv/gc/shared/barrierSetAssembler_riscv.cpp
@@ -308,9 +308,13 @@ void BarrierSetAssembler::nmethod_entry_barrier(MacroAssembler* masm, Label* slo
     Label skip_barrier;
     __ beq(t0, t1, skip_barrier);
 
-    int32_t offset = 0;
-    __ movptr(t0, StubRoutines::method_entry_barrier(), offset);
-    __ jalr(ra, t0, offset);
+    RuntimeAddress target(StubRoutines::method_entry_barrier());
+    __ relocate(target.rspec(), [&] {
+      int32_t offset;
+      __ la_patchable(t0, target, offset);
+      __ jalr(ra, t0, offset);
+    });
+
     __ j(skip_barrier);
 
     __ bind(local_guard);